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ics9248-92 idt tm mobile pentium ii tm system clock chip 309?01/25/10 mobile pentium ii tm system clock chip 1 datasheet recommended application: the ics9248-92 is a fully compliant timing solution for the intel mobile 440bx/mx chipset requirements. general description: features include two strong cpu, seven pci and eight sdram clocks. three reference outputs are available equal to the crystal frequency. stronger drive cpuclk outputs typically provide greater than 1 v/ns slew rate into 20pf loads. this device meets rise and fall requirements with 2 loads per cpu output (ie, one clock to cpu and nb chipset, one clock to two l2 cache inputs). pwr_dwn# pin allows low power mode by stopping crystal osc and pll stages. for optional power management, cpu_stop# can stop cpu (0:1) clocks and pci_stop# will stop pciclk (0:5) clocks. pciclk outputs typically provide better than 1v/ns slew rate into 30pf loads while maintaining 505% duty cycle. the ref clock outputs typically provide better than 0.5v/ns slew rates. the ics9248-92 accepts a 14.318mhz reference crystal or clock as its input and runs on a 3.3v core supply. features: ? generates system clocks for cpu, sdram, pci, plus 14.318 mhz ref(0:2), usb, plus super i/o i2c serial configuration interface provides output clock disabling and other functions mode input pin selects optional power management input control pins two fixed outputs separately selectable as 24 or 48mhz 2.5v outputs: cpu 3.3v outputs: sdram, pci, ref, 48/24 mhz no power supply sequence requirements uses external 14.318mhz crystal 48 pin 240 mil tssop package output enable register for serial port control: 1 = enable 0 = disable block diagram pin configuration functionality
idt tm mobile pentium ii tm system clock chip 309?01/25/10 ics9248-92 mobile pentium ii tm system clock chip 2 pin description power groups vddcor = supply for pll core vddref = ref [0:2], x1, x2 vddpci = pciclk_f, pciclk [0:5] vddsdr = sdram [0:7] vdd48 = 48/24mhza, 48/24mhz vddlcpu = cpuclk [0:1]
idt tm mobile pentium ii tm system clock chip 309?01/25/10 ics9248-92 mobile pentium ii tm system clock chip 3 power on conditions example: a) if mode = 1, pins 26 and 27 are configured as sdram7 and sdram6 respectively. b) if mode = 0, pins 26 and 27 are configured as pci_stop# and cpu_stop# respectively. power on default conditions at power-up and before device programming, all clocks will default to an enabled and ?on? condition. the frequencies that are t hen produced are on the mode pin as shown in the table below.
idt tm mobile pentium ii tm system clock chip 309?01/25/10 ics9248-92 mobile pentium ii tm system clock chip 4 general i 2 c serial interface information the information in this section assumes familiarity with i 2 c programming. for more information, contact idt for an i 2 c programming application note. how to write: controller (host) sends a start bit. controller (host) sends the write address d2 (h) ics clock will acknowledge controller (host) sends a dummy command code ics clock will acknowledge controller (host) sends a dummy byte count ics clock will acknowledge controller (host) starts sending first byte (byte 0) through byte 5 ics clock will acknowledge each byte one at a time . controller (host) sends a stop bit how to read: controller (host) will send start bit. controller (host) sends the read address d3 (h) ics clock will acknowledge ics clock will send the byte count controller (host) acknowledges ics clock sends first byte (byte 0) through byte 6 controller (host) will need to acknowledge each byte controller (host) will send a stop bit controller (host) ics (slave/receiver) st art bit address d2 (h ) ac k dummy command code ac k dummy byte count ac k byte 0 ac k byte 1 ac k byte 2 ac k byte 3 ac k b y te 4 ac k b y te 5 ac k b y te 6 ack stop bit how to write: controller (host) ics (slave/receiver) st art bit address d3 (h ) ac k byte coun t ack byte 0 ack byte 1 ack byte 2 ack byte 3 ack byte 4 ack byte 5 ack byte 6 ack stop bit how to read: n otes: 1. the ics clock generator is a slave/receiver, i 2 c component. it can read back the data stored in the latches for verification. read-back will support intel piix4 "block-read" protocol . 2. the data transfer rate supported by this clock generator is 100k bits/sec or less (standard mode) 3. the input is operating at 3.3v logic levels. 4. the data byte format is 8 bit bytes. 5. to simplify the clock generator i 2 c interface, the protocol is set to use only " block-writes " from the controller. the bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. the command code and byte count shown above must be sent, but the data is ignored for those two bytes. the data is loaded until a stop sequence is issued. 6. at power-on, all registers are set to a default condition, as shown.
idt tm mobile pentium ii tm system clock chip 309?01/25/10 ics9248-92 mobile pentium ii tm system clock chip 5 serial configuration command bitmaps byte 0: functional and frequency select clock register (default on bits 7, 6, 5, 4, 1, 0 = 0) note: pwd = power-up default select functions notes: 1. tclk is a test clock driven on the x1 (crystal in pin) input during test mode .
idt tm mobile pentium ii tm system clock chip 309?01/25/10 ics9248-92 mobile pentium ii tm system clock chip 6
idt tm mobile pentium ii tm system clock chip 309?01/25/10 ics9248-92 mobile pentium ii tm system clock chip 7 power management clock enable configuration full clock cycle timing is guaranteed at all times after the system has initially powered up except where noted. during power u p and power down operations using the pwr pd# select pin will not cause clocks of a short or longer pulse than that of the running cl ock. the first clock pulse coming out of a stopped clock condition may be slightly distorted due to clock network charging circuitry . board routing and signal loading may have a large impact on the initial clock distortion also. power management requirements notes. 1. clock on latency is defined from when the clock enable goes active to when the first valid clock comes out of the device. 2. clock off latency is defined from when the clock enable goes inactive to when the last clock is driven low out of the device . 3. power up latency is when pd# goes inactive (high) to when the first valid clocks are output by the device. 4. power down has controlled clock counts applicable to cpuclk, sdram, pciclk only. the ref will be stopped independant of these.
idt tm mobile pentium ii tm system clock chip 309?01/25/10 ics9248-92 mobile pentium ii tm system clock chip 8 cpu_stop# timing diagram cpustop# is an asychronous input to the clock synthesizer. it is used to turn off the cpuclks for low power operation. cpu_stop# is synchronized by the ics9248-92. the minimum that the cpuclk is enabled (cpu_stop# high pulse) is 100 cpuclks. all other clocks will continue to run while the cpuclks are disabled. the cpuclks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. cpuclk on latency is less than 4 cpuclks and cpuclk off latency is less than 4 cpuclks. notes: 1. all timing is referenced to the internal cpuclk. 2. cpu_stop# is an asynchronous input and metastable conditions may exist. this signal is synchronized to the cpuclks inside the ics9248-92. 3. all other clocks continue to run undisturbed. 4. pd# and pci_stop# are shown in a high (true) state.
idt tm mobile pentium ii tm system clock chip 309?01/25/10 ics9248-92 mobile pentium ii tm system clock chip 9 pci_stop# timing diagram pci_stop# is an asynchronous input to the ics9248-92. it is used to turn off the pciclk (0:5) clocks for low power operation. pci_stop# is synchronized by the ics9248-92 internally. the minimum that the pciclk (0:5) clocks are enabled (pci_stop# high pulse) is at least 10 pciclk (0:5) clocks. pciclk (0:5) clocks are stopped in a low state and started with a full high pul se width guaranteed. pciclk (0:5) clock on latency cycles are only one rising pciclk clock off latency is one pciclk clock. notes: 1. all timing is referenced to the internal cpuclk (defined as inside the ics9248 device.) 2. pci_stop# is an asynchronous input, and metastable conditions may exist. this signal is required to be synchronized inside the ics9248. 3. all other clocks continue to run undisturbed. 4. pd# and cpu_stop# are shown in a high (true) state.
idt tm mobile pentium ii tm system clock chip 309?01/25/10 ics9248-92 mobile pentium ii tm system clock chip 10 pd# timing diagram the power down selection is used to put the part into a very low power state without turning off the power to the part. pd# is an asynchronous active low input. this signal is synchronized internal by the ics9248-92 prior to its control action of powering down the clock synthesizer. internal clocks will not be running after the device is put in power down state. when pd# is active (low) all clocks are driven to a low state and held prior to turning off the vcos and the crystal oscillator. the pow er on latency is guaranteed to be less than 3ms. the power down latency is less than three cpuclk cycles. pci_stop# and cpu_stop# are don?t care signals during the power down operations. notes: 1. all timing is referenced to the internal cpuclk (defined as inside the ics9248 device). 2. pd# is an asynchronous input and metastable conditions may exist. this signal is synchronized inside the ics9248. 3. the shaded sections on the vco and the crystal signals indicate an active clock is being generated.
idt tm mobile pentium ii tm system clock chip 309?01/25/10 ics9248-92 mobile pentium ii tm system clock chip 11
idt tm mobile pentium ii tm system clock chip 309?01/25/10 ics9248-92 mobile pentium ii tm system clock chip 12
idt tm mobile pentium ii tm system clock chip 309?01/25/10 ics9248-92 mobile pentium ii tm system clock chip 13
idt tm mobile pentium ii tm system clock chip 309?01/25/10 ics9248-92 mobile pentium ii tm system clock chip 14 general layout precautions: 1) use a ground plane on the top routing layer of the pcb in all areas not used by traces. 2) make all power traces and ground traces as wide as the via pad for lower inductance. notes: 1) all clock outputs should have provisions for a 15pf capacitor between the clock output and series terminating resistor. not shown in all places to improve readability of diagram. 2) optional crystal load capacitors are recommended. they should be included in the layout but not inserted unless needed. component values: c1 : crystal load values determined by user c2 : 22pf/20v/d case/tantalum avx tajd226m020r c3 : 15pf capacitor fb = fair-rite products 2512066017x1 all unmarked capacitors are 0.01pf ceramic connections to vdd:
idt tm mobile pentium ii tm system clock chip 309?01/25/10 ics9248-92 mobile pentium ii tm system clock chip 15 ordering information 9248YG-92GLFT example: designation for tape and reel packaging lead free, rohs compliant package type g = tssop revision designator device type xxxx y g lf t index area index area 12 1 2 n d e1 e seating plane seating plane a1 a a2 e -c- - c - b c l aaa c min max min max a -- 1.20 -- .047 a1 0.05 0.15 .002 .006 a2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 d e e1 6.00 6.20 .236 .244 e l 0.45 0.75 .018 .030 n a 0808 aaa -- 0.10 -- .004 variations min max min max 48 12.40 12.60 .488 .496 10-0039 reference doc.: jedec publication 95, mo-153 in millimeters in inches common dimensions 0.50 basic 0.020 basic 8.10 basic 0.319 basic n d (inch) see variations see variations d mm. 48-lead, 6.10 mm. body, 0.50 mm. pitch tssop (240 mil) (20 mil) symbol see variations common dimensions see variations
ics9248-92 mobile pentium ii tm system clock chip 16 innovate with idt and accelerate your future networks. contact: www.idt.com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support 408-284-6578 pcclockhelp@idt.com corporate headquarters integrated device technology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800 345 7015 +408 284 8200 (outside u.s.) asia pacific and japan integrated device technology singapore (1997) pte. ltd. reg. no. 199707558g 435 orchard road #20-03 wisma atria singapore 238877 +65 6 887 5505 europe idt europe, limited prime house barnett wood lane leatherhead, surrey united kingdom kt22 7de +44 1372 363 339 ? 2009 integrated device technology , inc. all rights reserved. product specifications subject to change without notice. idt, ic s, and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other br ands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa tm

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